1. Field of the Invention
The present invention relates to a semiconductor device with a self-aligned silicide (SALICIDE) structure and a fabrication method thereof and more particularly, to a semiconductor device equipped with nonvolatile memory cells formed by Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and a peripheral circuitry including MOSFETs on a semiconductor substrate, in which the MOSFETs of the peripheral circuitry have silicide layers at their source/drain regions while the MOSFETs of the memory cells have no silicide layers at their source/drain regions, and a fabrication method of the semiconductor device.
2. Description of the Prior Art
Conventionally, the miniaturization and integration of semiconductor elements and components have been progressing perpetually in semiconductor integrated circuit devices.
In recent years, highly-integrated semiconductor integrated circuit devices (i.e., LSIs) designed according to the design rule as small as 0.15 to 0.25 .mu.m, such as memory devices and logic devices, have been fabricated and actually used. These LSIs are often constituted by the use of MOSFETs, because MOSFETs are miniaturized more readily than bipolar transistors.
According to the progressing integration of the semiconductor elements and components in the LSIs, there has been the need to decrease the length of the gate electrodes and the width of the source/drain regions in the MOSFETs. However, the decrease in the length of the gate electrodes and the width of the source/drain regions increases their electric resistance and as a result, there arises a problem that the operation speed of the inner circuits of the LSIs tends to be badly affected.
To solve this problem, refractory silicide layers, which are low in electric resistance, have been widely used for the source/drain regions formed in a single-crystal silicon (Si) substrate and the gate electrodes made of polycrystalline Si (i.e., polysilicon) in the miniaturized MOSFETs. The refractory silicide layers are typically located on the surface areas of the source/drain regions and the gate electrodes.
The silicide layers are typically formed by the use of the well-known SALICIDE technique. Specifically, first, a refractory metal such as a titanium (Ti) film is formed in contact with the single-crystal Si source/drain regions and the polysilicon gate electrodes. Then, the refractory metal film, the source/drain regions, and the gate electrodes are heat-treated to cause a silicidation reaction between the refractory metal and Si. Thus, refractory silicide films are formed at the surface areas of the source/drain regions, and the gate electrodes, respectively. Finally, the unreacted refractory metal film is removed. Since the refractory silicide films are formed in self-alignment to the gate electrodes and an isolation dielectric without any masking film, this formation method is termed the "self-aligned silicide" technique, or the "SALICIDE" technique. Also, the source/drain regions and the gate electrodes equipped with the silicide films thus formed are termed the "SALICIDE" structure.
FIGS. 1A to 1K show a conventional fabrication method of a flush nonvolatile semiconductor memory device which is termed a flush Electrically Erasable Programmable Read-Only Memory (EEPROM), in which the SALICIDE technique is used.
This memory device is comprised of a lot of nonvolatile memory cells formed by n-channel MOSFETs with floating gates and a peripheral circuitry formed by n- and p-channel MOSFETs. Therefore, the peripheral circuitry has the Complementary MOS (CMOS) structure. The peripheral circuitry serves to provide control operations for the memory cells, such as the reading operation and the writing or reprogramming operation. The memory cells are arranged in a matrix array in a memory cell area. The n- and p-channel MOSFETs of the peripheral circuitry are arranged in peripheral NMOS and PMOS areas, respectively.
In FIGS. 1A to 1K, however, two adjoining ones of the n-channel MOSFETs in the memory cells, one of the n-channel MOSFETs in the peripheral circuitry, and one of the p-channel MOSFETs in the peripheral circuitry are explained below for the sake of simplification of description.
First, as shown in FIG. 1A, an isolation dielectric 102 with a specific depth is selectively formed at the main surface of a p- or n-type single-crystal Si substrate 101 by the well-known Local Oxidation of Silicon (LOCOS) process, thereby defining a peripheral NMOS area 151 and a peripheral PMOS area 152 of the peripheral circuitry and a memory cell area 153.
Next, a patterned photoresist film 103a with a window uncovering the peripheral NMOS area 151 is formed using a photolithography technique. Then, using the photoresist film 103a as a mask, boron (B) is selectively ion-implanted into the substrate 101, thereby forming a p-type well 104 in the peripheral NMOS area 151, as shown in FIG. 1B. Thereafter, the photoresist film 103a is removed.
In the same way as that of the p-type well 104, an n-type well 105 is formed in the peripheral PMOS area 152 and a p-type well 106 is formed in the memory cell area 153, as shown in FIG. 1C.
A silicon dioxide (SiO.sub.2) film 137 is formed on the whole main surface of the substrate 101 by a thermal oxidation process, as shown in FIG. 1D. By successive Chemical Vapor Deposition (CVD) processes, a polysilicon film 138 (approximately 150 nm in thickness) is formed on the whole SiO.sub.2 film 137, an ONO film 139 is formed on the whole polysilicon film 138, and a tungsten polycide film 140 is formed on the whole ONO film 139. The ONO film 139 is formed by three stacked subfilms, i.e., a SiO.sub.2 subfilm, a silicon nitride (Si.sub.3 N.sub.4) sub film, and a SiO.sub.2 subfilm. The tungsten polycide film 140 is a composite film of an impurity-doped polysilicon subfilm and a tungsten silicide subfilm, where the impurity is typically phosphorus (P).
Thereafter, a patterned photoresist film 103b with a pattern covering the areas for gate electrodes is formed using a photolithography technique. Then, using the photoresist film 103b as a mask, the polysilicon film 138, the ONO film 139, and the tungsten polycide film 140 are successively patterned, thereby forming gate electrodes 111 for the n-channel MOSFETs arranged in the memory cell area 153, as shown in FIG. 1E. The gate electrodes 111 are formed by the combination of the remaining polysilicon film 138, the remaining ONO film 139, and the remaining tungsten polycide film 140. In this patterning process, the SiO.sub.2 film 137 is not patterned.
A polysilicon film (not shown) is formed on the whole SiO.sub.2 film 137 to cover the whole substrate 101 and then, the polysilicon film is patterned to form gate electrodes 112 for the n- and p-channel MOSFETs in the peripheral NMOS and PMOS regions 151 and 152. In this patterning process, the SiO.sub.2 film 137 is not patterned.
The SiO.sub.2 film 137 is selectively etched using the gate electrodes 111 and 112 as a mask, thereby forming respective gate oxide films 107 and 108. The state at this stage is shown in FIG. 1E.
Following this step, a SiO.sub.2 film (not shown) is formed on the uncovered main surface of the substrate 101 to cover the gate electrodes 111 and 112 by a CVD process. The SiO.sub.2 film is then etched back by an anisotropic etching process, thereby forming sidewall spacers 113 at each side of the gate electrodes 111 and 112, as shown in FIG. 1F.
An n-type impurity such as arsenic (As) is selectively ion-implanted into the p-type wells 104 and 106 while covering the peripheral PMOS area 152 by a mask. Thus, the n-type impurity is selectively implanted into the p-type wells 104 and 106 in self-alignment to the gate electrodes 111 and 112, the sidewall spacers 113, and the isolation dielectric 102.
In the same way as the p-type wells 104 and 106, a p-type impurity such as boron (B) is selectively ion-implanted into the n-type well 105 while covering the peripheral NMOS area 151 and the memory cell area 153 by a mask. Thus, the p-type impurity is selectively implanted into the n-type well 105 in self-alignment to the gate electrodes 111 and 112, the sidewall spacers 113, and the isolation dielectric 102.
After an annealing process at a temperature of 800 to 1000.degree. C., n-type source/drain regions 114 are formed in the p-type well 104, p-type source/drain regions 115 are formed in the n-type well 105, and n-type source/drain regions 114 are formed in the p-type well 106. The state at this stage is shown in FIG. 1F.
Subsequently, as shown in FIG. 1G, a titanium (Ti) film 116 with a thickness of approximately 50 nm is formed over the whole surface of the substrate 101. The substrate 101 with the Ti film 116 is subjected to a heat treatment in a nitrogen (N.sub.2) atmosphere with a normal pressure at a temperature of 600 to 650.degree. C. for 30 to 60 seconds using a heat treatment apparatus such as a lamp annealing apparatus.
Thus, nitrogen atoms are diffused into the Ti film 116 to thereby form a nitrogen-containing Ti film 119, as shown in FIG. 1H. At the same time as this, the single-crystal Si source/drain regions 114 and 115 and the gate electrodes 112 chemically react with the nitrogen-containing Ti film 119, resulting in titanium silicide (TiSi.sub.2) films 117a and 117b due to a silicidation reaction. The TiSi.sub.2 films 117a are located at the surfaces of the source/drain regions 114 and 115. The TiSi.sub.2 films 117b are located at the surfaces of the gate electrodes 112.
The TiSi.sub.2 films 117a and 117b, which has the C49 phase, has a comparatively high electric resistance of approximately 60 .mu..OMEGA..multidot.cm.
After this heat treatment process for silicidation, the unreacted nitrogen-containing Ti film 119 is removed by a wet etching process using a mixture of water solutions of ammuonia (NH.sub.3) and hydrogen peroxide (H.sub.2 O.sub.2). Thus, the TiS.sub.2 i films 117a and to 117b are selectively left on the substrate 101, as shown in FIG. 1I.
The substrate 101 with the TiSi.sub.2 films 117a and 117b is then subjected to another heat treatment in a nitrogen (N.sub.2) atmosphere with a normal pressure at a temperature of approximately 850.degree. C. for approximately 60 seconds using a heat treatment apparatus such as a lamp annealing apparatus. Thus, the TiSi.sub.2 films 117a and 117b having the C49 phase are turned to have the C54 phase due to phase transition.
The TiSi.sub.2 films 117a and 117b having the C54 phase has a comparatively low electric resistance of approximately 20 .mu..OMEGA..multidot.cm.
A thick SiO.sub.2 film 120 serving as an interlevel dielectric is formed to cover the whole surface of the substrate 101 by a CVD process. Then, the surface of the SiO.sub.2 film 120 is planarized by a Chemical Mechanical Polishing (CMP) process, as shown in FIG. 1J.
Then, as shown in FIG. 1K, via holes 123 are formed to penetrate through the SiO.sub.2 film 120 by using photolithography and etching techniques to the source/drain regions 114 and 115 and the gate electrodes 111 and 112. Metallic plugs 121 are filled in the via holes 123 to be contacted with the source/drain regions 114 and 115 and the gate electrodes 111 and 112 by a selective growth process of a metal film.
Finally, an aluminum (Al) film (not shown) is formed on the SiO.sub.2 film 120 and then, it is patterned to form wiring lines 122 to be contacted with the metallic plugs 121. Thus, the source/drain regions 114 and 115 and the gate electrodes 111 and 112 are electrically connected to the wiring lines 122.
Through the above-described process steps, the conventional flush nonvolatile semiconductor memory device is completed.
As seen from FIG. 1K, the n-type source/drain regions 114 having the silicide films 117a, the gate oxide film 107, the gate electrode 112 having the silicide films 117b, and the sidewall spacers 113 located in the peripheral NMOS area 151 constitute an n-channel MOSFET 161 of the peripheral circuitry. The p-type source/drain regions 115 having the silicide films 117a, the gate oxide film 107, the gate electrode 112 having the silicide films 117b, and the sidewall spacers 113 located in the peripheral PMOS area 152 constitute a p-channel MOSFET 162 of the peripheral circuitry. The n-type source/drain regions 114 having the silicide films 117a, the gate oxide film 107, the gate electrode 111, and the sidewall spacers 113 located in the memory cell area 153 constitute n-channel MOSFETs 163 of the memory cell array.
With the conventional fabrication method of the flush nonvolatile semiconductor memory device shown in FIGS. 1A to 1K, to improve the performance of the memory device while thinning the refractory silicide films 117a and 117b of the MOSFETs in the peripheral NMOS and PMOS areas 151 and 152, there is the following problem.
Specifically, when electrons are drawn out from the floating gates 108 to the source/drain regions 114 of the MOSFETs 163 in the memory cell area 153, the drawing speed of the electrons need to be as high as possible. From this point of view, it is preferred that the doping concentration of the source/drain regions 114 is set as high as possible. In this case, however, there is a problem that refractory silicide tends to be difficult to be produced if arsenic (As) is used as the n-type impurity for the source/drain regions 114. This is because the silicidation reaction is suppressed by the arsenic impurity doped into the regions 114 and as a consequence, the nitriding reaction becomes superior to the silicidation reaction.
There are two solutions to solve this problem. A first one of the solutions is to decrease the doping (i.e., As) concentration of the source/drain regions 114. A second one of the solutions is to increase the thickness of the Ti film 116, thereby suppressing the competition or conflict between the nitriding and silicidation reactions.
With the first one of the solutions, however, as disclosed in an article written by Y. Tang et al., IEEE ELECTRON DEVICE LETTERS, Vol. 17, No. 11, pp 525-527, November 1996, the Fowler-Nordheim tunneling current becomes small. This lowers the drawing speed of the electrons from the floating gates 108, thereby delaying the operation speed of the memory device.
With the second one of the solutions, the TiSi.sub.2 films 117aand 117b become thicker according to the thickness increase of the Ti film 116. Therefore, the shallow p-n junctions of the source/drain regions 114 and 115 occurring due to the device miniaturization tendency approach the TiSi.sub.2 films 117a and 117b, resulting in increase of the current leakage. This means that the thickness increase of the Ti film 116 is contrary to the requirement to decrease the thickness of the TiSi.sub.2, films 117a and 117b. Accordingly, the second one of the solutions is unable to be adopted for this purpose.